Method and apparatus for memory redundancy with no critical delay-path

ABSTRACT

A memory redundancy scheme is provided for re-routing data signal paths to disconnect defective memory blocks in a memory array. Each memory block is provided with a corresponding routing unit. Each routing unit is coupled to its corresponding memory block and at least one additional adjacent memory block. The routing units are configured to route data between functional memory blocks and a data bus. The routing units are controlled by configuration values stored in a shifter circuit, which extends through the routing units. To replace a defective memory block, the address of the defective memory block is identified. Configuration values are serially loaded into the shifter circuit, wherein the configuration values are selected in response to the address of the defective memory block. The configuration values cause the routing units to bypass the defective memory block, connect a redundant memory block, and shift connections in the memory blocks located between the redundant memory block and the defective memory block.

RELATED APPLICATIONS

The present application is a continuation-in-part of U.S. patent application Ser. No. 09/256,746, by Wingyu Leung and Jui-Pin Tang, filed Feb. 24, 1999, now abandoned.

FIELD OF THE INVENTION

The present invention is related to semiconductor memories. In particular, the present invention relates to the implementation of column redundancy for semiconductor memories, whereby defective columns of a memory array are replaced with redundant columns.

DISCUSSION OF RELATED ART

A semiconductor memory typically includes redundant circuitry to increase the functional yield. In general, the redundant circuitry can be classified as row redundant circuitry or column redundant circuitry. Row redundant circuitry includes one or more redundant rows of memory cells and the associated circuitry required to activate the redundant rows and de-activate defective rows of memory cells. Similarly, column redundant circuitry includes one or multiple redundant columns of memory cells and the associated circuitry required to activate the redundant columns and de-activate defective columns of memory cells.

Most conventional column redundancy schemes use one or more dedicated redundant blocks, which can be used to repair any defective blocks. Each redundant block is coupled in parallel with the normal blocks by a programmable element, such as a fuse or anti-fuse. The programmable elements are used to selectively connect the read and write data terminals to a normal block or a redundant block. Each redundant block is capable of being connected to the read and write data terminals associated with any one of the normal blocks. Because each redundant block must be capable of connection to every normal block, long routing paths exist between the redundant blocks and the normal blocks. The long routing paths can create speed critical paths for the memory. Such a column redundancy scheme is illustrated in FIG. 1.

FIG. 1 is a schematic diagram of a memory circuit 100 that implements a conventional redundancy scheme. Memory circuit 100 includes a memory cell array 101 having a plurality of rows and columns. Memory cell array 101 is subdivided into 130 memory blocks MB₁₂₉-MB₀. Each of the memory blocks MB₁₂₉-MB₀ includes 8 columns and 1024 rows of memory cells. If memory blocks MB₁₂₇-MB₀ are not defective, these memory blocks are accessed during the normal operation of memory circuit 100. Memory blocks MB₁₂₉ and MB₁₂₈ are redundant memory blocks that are used to replace up to two defective memory blocks.

Each of memory blocks MB₁₂₉-M₀ is coupled to a corresponding 8-to-1 column decoder CD₁₂₉-CD₀. Each of column decoders CD₁₂₉-CD₀ is coupled to a corresponding data line D₁₂₉-D₀. Data lines D₁₂₉-D₀ normally carry data signals D[129:0], respectively. Each of column decoders CD₁₂₉-CD₀ is controlled to couple one of the eight columns in its corresponding memory block to its corresponding data line. For example, column decoder CD₃ couples one of the eight columns of memory block MB₃ to data line D₃.

Each of data lines D₁₂₇-D₀ includes a fuse that can be blown if the associated memory block or column decoder is defective. For example, data line D₃ includes fuse 103.

Column decoders CD₁₂₉ and CD₁₂₈ are coupled to redundant data lines D₁₂₉ and D₁₂₈, respectively. These redundant data lines D₁₂₉ and D₁₂₈ extend the width of the memory circuit 100, traversing data lines D₁₂₇-D₀. An anti-fuse is provided between each of redundant data lines D₁₂₉-D₁₂₈ and each of the normal data lines D₁₂₇-D₀. For example, anti-fuse 104 is coupled between redundant data line D₁₂₈ and data line D₃. Similarly, anti-fuse 105 is coupled between redundant data line D₁₂₉ and data line D₃.

If all of memory blocks MB₁₂₇-MB₀ and column decoders CD₁₂₇-CD₀ are free of defects, then none of the fuses or anti-fuses are blown. As a result, column decoders CD₁₂₇-CD₀ are coupled to data lines D₁₂₇-D₀, respectively. However, if one of memory blocks MB₁₂₇-MB₀ or column decoders CD₁₂₇-CD₀ is defective, then the fuse associated with the defective memory block/column decoder is blown, thereby de-coupling the defective memory block/column decoder from its associated data line. An associated anti-fuse is then blown to couple the isolated data line to one of the redundant data lines.

For example, if memory block MB₃ is defective, then fuse 103 is blown to de-couple memory block M₃ and column decoder CD₃ from data line D₃. Anti-fuse 104 is then blown, thereby coupling data line D₃ to redundant data line D₁₂₈. Under these conditions, redundant memory block MB₁₂₈ and redundant column decoder CD₁₂₈ provide service to data line D₃. Redundant memory block MB₁₂₉ and redundant column decoder CD₁₂₉ can replace a second defective memory block/column decoder in a similar manner.

When redundant data lines D₁₂₉ and D₁₂₈ are used to route data values, relatively long interconnection delays can exist because of the length of these redundant data lines. In the example described above, the path from data line D₃ to column decoder CD₁₂₈ is much longer than any of the other data paths. This interconnection delay becomes intolerable as the ratio of the number of normal columns to the number of redundant columns increases, especially in embedded memory design. The long interconnection delay can create a critical path that effectively increases the access time of memory circuit 100.

It would therefore be desirable to have a memory system that provides redundancy without adding excessive interconnection delays.

SUMMARY

Accordingly, the present invention provides a memory redundancy scheme for re-routing the data signal paths to disconnect defective memory blocks within a memory array. To implement the redundancy scheme, each of the memory blocks is provided with a corresponding routing control unit. Each of the routing control units includes a fuse which is blown if the corresponding memory block is defective. The routing control units are connected in a chain. A code signal having predetermined default value is provided to a routing control unit at the end of the chain. The code signal is routed along the chain through the routing control units. The code signal is passed through each routing control unit unchanged, unless the routing control unit has a blown fuse. In this case, the routing control unit modifies the code signal. The modified code signal is then passed to the next routing control unit in the chain. In this manner, each routing control unit receives information for all the previous fuses in the chain, adds its own fuse information, and then passes a representative code signal to the next routing control unit. Each routing control unit selects a data signal path in response to its received code signal and the state of its fuse. If the code signal indicates the presence of a defective memory block, the data signal path is modified such that data signals are re-routed to the next or previous memory blocks, depending on the memory array function (read or write). Thus, logically, a defective memory block is disconnected from the original data signal path and replaced by a neighboring memory block. Because each data signal path is only re-routed at most by one (or two) memory blocks, the delays on the various data signal paths are substantially identical. Moreover, the access time with the redundancy scheme is approximately the same as the access time of a memory system without a redundancy scheme. In addition, the above-described process only needs to be performed once after power-on reset. As a result, the normal operation of the memory array will not be affected by the redundancy scheme.

In another embodiment of the present invention, a memory redundancy scheme is provided for re-routing data signal paths to disconnect defective memory blocks in a memory array. Each memory block is provided with a corresponding routing unit. Each routing unit is coupled to its corresponding memory block and at least one additional adjacent memory block. The routing units are configured to route data between functional memory blocks and a data bus. The routing units are controlled by configuration values stored in a shifter circuit, which extends through the routing units. To replace a defective memory block, the address of the defective memory block is identified. Configuration values are serially loaded into the shifter circuit, wherein the configuration values are selected in response to the address of the defective memory block. The configuration values cause the routing units to bypass the defective memory block, connect a redundant memory block, and shift connections in the memory blocks located between the redundant memory block and the defective memory block.

The present invention will be more fully understood in view of the following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional memory circuit that has a redundancy scheme that uses relatively long interconnection delay paths;

FIG. 2 is a block diagram of a memory system that implements a read redundancy scheme accordance with one embodiment of the present invention;

FIG. 3 is a block diagram of a read routing control unit in accordance with one embodiment of the present invention;

FIG. 4 is a block diagram of a portion of memory system that implements a write redundancy scheme in accordance with one embodiment of the invention;

FIG. 5 is a schematic diagram of a write routing control unit in accordance with one embodiment of the present invention;

FIG. 6 is a block diagram of a byte write masking circuit in accordance with one embodiment of the present invention;

FIG. 7 is a schematic diagram of a mask routing control unit in accordance with one embodiment of the present invention;

FIG. 8 is a block diagram of a memory system that implements a bank redundancy scheme in accordance with one embodiment of the present invention;

FIG. 9 is a schematic diagram of a bank routing control unit in accordance with one embodiment of the present invention;

FIG. 10A is a block diagram of a memory system that implements a read and write redundancy scheme accordance with another embodiment of the present invention;

FIG. 10b is a block diagram of an expanded memory system that implements a read and write redundancy scheme accordance with another embodiment of the present invention;

FIG. 11 is a circuit diagram of a read/write routing control unit used in a system having two redundant memory block/column decoder pairs;

FIG. 12 is a circuit diagram of a routing unit that is used in a system having three redundant memory block/column decoder pairs;

FIG. 13 is a block diagram of routing unit programmer for programming the shift chain of the routing units of FIG. 10A in accordance with one embodiment of the present invention;

FIG. 14 is a circuit diagram of a routing unit for separately routing read and write data from and to a set of memory blocks in accordance with another embodiment of the invention; and

FIG. 15 is a circuit diagram of a routing unit for separately routing write data and write masking information in accordance with another embodiment of the present invention.

DETAILED DESCRIPTION

FIG. 2 is a block diagram of a portion of a memory system 200 that implements a read redundancy scheme in accordance with one embodiment of the present invention. Memory system 200 includes a memory cell array 201 having a plurality of rows and columns. Memory cell array 201 is subdivided into 130 memory blocks MB₁₂₉-MB₀. Each of the memory blocks MB₁₂₉-MB₀ includes 8 columns and 1024 rows of memory cells.

Each of memory blocks MB₁₂₉-M₀ is coupled to a corresponding 8-to-1 column decoder CD₁₂₉-CD₀. Each of column decoders CD₁₂₉-CD₀ is coupled to a corresponding data line D₁₂₉-D₀. Data lines D₁₂₉-D₀ carry data signals D[129:0], respectively. Each of column decoders CD₁₂₉-CD₀ is controlled to couple one of the eight columns in its corresponding memory block to its corresponding data line. For example, column decoder CD₃ couples one of the eight columns of memory block MB₃ to data line D₃.

Memory system 200 also includes read routing control units RRCU₁₂₇-RRCU₀, which route data values from column decoders CD₁₂₉-CD₀ to output data lines DQ₁₂₇-DQ₀ as output data values DQ[127:0]. Each of the 128 read routing control units RRCU₁₂₇-RRCU₀ is coupled to a corresponding one of the 128 output data lines DQ₁₂₇-DQ₀.

As described above, there are two more memory block/column decoder pairs (130) than read routing control units (128). As described in more detail below, the two additional memory block/column decoder pairs allow up to two defective memory block/column decoder pairs to be replaced.

Each of the read routing control units RRCU₁₂₇-RRCU₀ is coupled to receive three data values from three consecutive column decoder circuits. More specifically, each read routing control unit RRCU_(N) is coupled to receive a first data value D[N] from a corresponding column decoder CD_(N), a second data value D[N+1] from a first subsequent read routing control unit RRCU_(N+1), and a third data value D[N+2] from a second subsequent read routing control unit RRCU_(N+2). For example, read routing control unit RRCU₀ receives data value D[0] from column decoder CD₀, data value D[1] from column decoder CD₁, and data value D[2] from column decoder CD₂. Each read routing control unit routes one of the three received data values to its associated output data line. Thus, read routing control unit RRCU₀ routes one of the data values D[0], D[1] or D[2] to output data line DQ₀.

If none of memory blocks MB₁₂₇-MB₀ or column decoders CD₁₂₇-CD₀ is defective, then data values D[127:0] are routed through read routing control units RRCU₁₂₇-RRCU₀, respectively. In this case, redundant memory blocks MB₁₂₉-MB₁₂₈ and redundant column decoders CD₁₂₉-CD₁₂₈ are not used.

If one of memory blocks MB₁₂₇-MB₀ or column decoders CD₁₂₇-CD₀ is defective, then the data value associated with the defective memory block/column decoder pair is not routed through the corresponding read routing control unit. Instead, the data value associated with the first subsequent memory block/column decoder pair is routed through the read routing control unit associated with the defective memory block/column decoder pair (assuming that the subsequent memory block/column decoder pair is not defective).

If the subsequent memory block/column decoder pair is also defective, then the data value associated with the second subsequent memory block/column decoder pair is routed through the read routing control unit associated with the original defective memory block/column decoder pair.

For example, if memory block MB₁ and/or column decoder CD₁ is defective, then read routing control unit RRCU₁ routes the data value D[2] from column decoder CD₂ as output data value DQ[1]. This allows memory block MB₂ and column decoder CD₂ to replace memory block MB₁ and column decoder CD₁. Read routing control unit RRCU₂ then routes the data value D[3] from column decoder CD₃ as output value DQ[2]. This allows memory block MB₃ and column decoder CD₃ to replace memory block MB₂ and column decoder CD₂. In this example, each of read routing control units RRCU₁₂₇-RRCU₁ routes a data value from a subsequent memory block/column decoder pair. Thus, at the left-most edge of memory system 200, read routing control unit RRCU₁₂₇ routes the data value D[128] from redundant memory block MB₁₂₈ and redundant column decoder CD₁₂₈ as output value DQ[127].

If both memory block/column decoder pair MB₁/CD₁ and memory block/column decoder pair MB₂/CD₂ are defective, then read routing control unit RRCU₁ routes the data value D[3] from column decoder CD₃ as output value DQ[1], and read routing control unit RRCU₂ routes the data value D[4] from column decoder CD₄ as output value DQ[2]. In this example, each of read routing control units RRCU₁₂₇-RRCU₁ routes a data value from a second subsequent memory block/column decoder pair. Thus, at the left-most edge of memory system 200, read routing control unit RRCU₁₂₇ routes the data value D[129] from redundant memory block MB₁₂₉ and redundant column decoder CD₁₂₉ as output value DQ[127].

In this manner, up to two defective memory block/column decoder pairs can be replaced using redundant memory blocks MB₁₂₉-MB₁₂₈ and redundant column decoders CD₁₂₉-CD₁₂₈. At most, data values from the column decoders CD₁₂₉-CD₀ are shifted to the right by two read routing control units. As a result, the delays in transmitting data values D[129:0] from column decoders CD₁₂₉-CD₀ to output lines DQ₁₂₇-DQ₀ are approximately equal, even under worst case routing conditions. That is, no routing paths are significantly longer than any other routing paths, regardless of which memory block/column decoder pairs are defective.

Note that the present invention is capable of replacing any two defective memory block/column decoder pairs, and not just two adjacent defective memory block/column decoder pairs. For example, assume that memory blocks MB₂ and MB₁₂₆ are defective. In this case, read routing control units RRCU₁ and RRCU₀ are controlled to route the data values D[1] and D[0], respectively, from column decoders CD₁ and CD₀, respectively, as output values DQ[1] and DQ[0], respectively. Because memory block MB₂ is defective, read routing control units RRCU₁₂₄-RRCU₂ are controlled to route the data values D[125]-D[3], respectively, from column decoders CD₁₂₅-CD₃, respectively, as output values DQ[124]-DQ[2], respectively. Because memory block MB₁₂₆ is also defective, read routing control units RRCU₁₂₇-RRCU₁₂₅ are controlled to route the data values D[129]-D[127], respectively, from column decoders CD₁₂₉-CD₁₂₇, respectively, as output values DQ[127]-DQ[125], respectively.

FIG. 3 is a block diagram of read routing control unit RRCU₀ in accordance with one embodiment of the present invention. Read routing control unit RRCU₀ includes inverters 301-306, p-channel transistor 307, n-channel transistor 308, fuse 309 and switches 311-316. Inverters 302 and 303 are cross-coupled to form latch 310. In the described example, read routing control units RRCU₁₂₇-RRCU₁ are identical to read routing control unit RRCU₀.

Data values D[0], D[1] and D[2] from column decoders CD₀, CD₁ and CD₂ are provided to input terminals DI₀, DI₁ and DI₂, respectively, of read routing control unit RRCU₀. These data values D[0], D[1] and D[2] are provided to switches 313, 314 and 315, respectively. As described in more detail below, one of these switches 313-315 is closed, thereby routing one of the three data values D[0], D[1] or D[2] as output value DQ[0]. In general, if memory block/column decoder pair MB₀/CD₀ is not defective, then switch 313 is closed, thereby routing data value D[0] as output value DQ[0]. If memory block/column decoder pair MB₀/CD₀ is defective, and first subsequent memory block/column decoder pair MB₁/CD₁ is not defective, then switch 314 is closed, thereby routing data value D[1] as output value DQ[0]. If the first subsequent memory block/column decoder pair MB₁/CD₁ is also defective, then switch 315 is closed, thereby routing data value D[2] as output value DQ[0].

Switches 313-315 are controlled as follows. During wafer test, memory blocks MB₁₂₉-MB₀ and column decoders CD₁₂₉-CD₀ are tested to determine whether these elements are defective or functional. If a memory block/column decoder pair is defective, then the fuse in the associated read routing control unit is blown. For example, if memory block/column decoder pair MB₀/CD₀ is defective, then fuse 309 in read routing control unit RRCU₀ is blown.

When memory system 200 is powered up, a logic high reset signal RST is applied to each of read routing control units RRCU₁₂₇-RRCU₀. Inverter 301 inverts the logic high RST signal, thereby providing a logic low signal to the gate of p-channel transistor 307. Under these conditions, p-channel transistor 307 turns on, thereby providing the V_(DD) supply voltage to latch 310. At this time, latch 310 stores a logic high value. The reset signal RST is then de-asserted low, thereby causing inverter 301 to provide a logic high signal to the gates of transistors 307 and 308. Under these conditions, p-channel transistor 307 is turned off, and n-channel transistor 308 is turned on. If fuse 309 is not blown, then turned on transistor 308 provides a logic low signal to latch 310, thereby causing latch 310 to store a logic low value. However, if fuse 309 is blown, then turned on transistor 308 has no effect on the state of latch 310. Thus, latch 310 continues to store a logic high value.

The value stored by latch 310 is provided to inverter 304. In response, inverter 304 provides a control signal GOOD. The GOOD control signal will have a logic high value if the associated memory block/column decoder pair MB₀/CD₀ is functional. Conversely, the GOOD control signal will have a logic low value if the associated memory block/column decoder pair MB₀/CD₀ is defective. Inverter 305 provides a control signal, which is the inverse of the GOOD control signal, to switch 312.

Switch 311 is coupled to receive a 3-bit initial input code signal C₀. Within read routing control unit RRCU₀, the initial input code signal C₀ is designated C_(I)[2:0]. The initial input code signal C₀, which has a value of [0,0,V_(DD)], is routed to switch 311 (as signal C_(I)[2:0]). The two least significant bits of signal C_(I)[2:0] (i.e., C_(I)[1:0]) are routed to switch 312, along with a logic “0” bit (i.e., ground). This routing is performed such that bits C_(I)[1:0] are the most significant bits provided to switch 312, and the logic “0” bit is the least significant bit provided to switch 312. Consequently, switch 312 is coupled to receive a value of [0,V_(DD),0]. Note that the V_(DD) signal is shifted to the left by one position in the value provided to switch 312.

If the GOOD control signal has a logic high value, switch 311 is closed and switch 312 is opened. Under these conditions, the input code signal C_(I)[2:0] of [0,0,V_(DD)] is routed as an output code signal C_(O)[2:0]. Output code bit C_(O)[0], which has a value of V_(DD), is provided to switch 313, thereby causing this switch to close. As a result, data value D[0] is routed to output terminal DO as output value DQ[0]. Note that both of switches 314 and 315 receive logic low values under these conditions, thereby turning off these switches. In summary, if the memory block MB₀ and column decoder CD₀ are both functional, then read routing control unit RRCU₀ routes the associated data value D[0] as output data value DQ[0].

If the GOOD signal has a logic low value, switch 312 is closed and switch 311 is opened. Under these conditions, an input code signal of [0,V_(DD),0] is routed through switch 312 as the output code signal C_(O)[2:0]. Output code bit C_(O)[0], which has a logic low value, is provided to switch 313, thereby opening this switch and preventing data value D[0] from being routed to output terminal DO as output value DQ[0].

Switch 316 is coupled to receive output code bits C_(O)[2:1], which in the present example have values of [0,V_(DD)]. Switch 317 is coupled to receive output code bit C_(O)[1] and a logic “0” bit (i.e., ground), which in the present example, have values of [V_(DD),0]. Switches 316 and 317 are operated in response to a control signal GOOD_(S). More specifically, control signal GOOD_(S) controls switch 316, and the inverse of control signal GOOD_(S) controls switch 317. Control signal GOOD_(S) is the GOOD control signal generated by the subsequent read routing control unit RRCU₁.

If the subsequent memory block/column decoder pair MB₁/CD₁ pair is functional, then control signal GOOD_(S) will have a logic high value, thereby closing switch 316 (and opening switch 317). Under these conditions, output code bits C_(O)[2:1] are routed as internal code bits C[2:1] to switches 315 and 314, respectively. Internal code bits C[2:1] therefore have values of [0,V_(DD)]. As a result, switch 314 is closed, thereby routing data value D[1] to output terminal DO as output value DQ[0]. In summary, if the memory block/column decoder pair MB₀/CD₀ is defective, and subsequent memory block/column decoder pair MB₁/CD₁ is functional, then read routing control unit RRCU₀ routes the data value D[1] as output data value DQ[0].

If memory block/column decoder pair MB₀/CD₀ pair is defective, and the subsequent memory block/column decoder pair MB₁/CD₁ pair is also defective, then control signal GOOD_(S) will have a logic low value, thereby closing switch 317 (and opening switch 316). Under these conditions, output code bit C_(O)[1] and the ground supply are routed as internal code bits C[2:1] to switches 315 and 314, respectively. Internal code bits C[2:1] therefore have values of [V_(DD),0]. As a result, switch 315 is closed, thereby routing data value D[2] to output terminal DO as output value DQ[0]. In summary, if the memory block/column decoder pairs MB₀/CD₀ and MB₁/CD₁ are both defective, then read routing control unit RRCU₀ routes the data value D[2] as output data value DQ[0].

Note that the 3-bit code signal provided as an input code signal to each read routing control unit RRCU_(N) is labeled as code signal C_(N), and that the 3-bit code signal provided as an output signal from each read routing control unit RRCU_(N) is labeled as code signal C_(N+1). Thus, read routing control unit RRCU₀ receives input code signal C₀ and provides output code signal C₁.

FIG. 4 is a block diagram of a portion of memory system 200 that implements a write redundancy scheme in accordance with one embodiment of the invention. As illustrated in FIG. 4, memory system 200 additionally includes write routing control units WRCU₁₂₉-WRCU₀, which route data values DQ[127:0] from data lines DQ₁₂₇-DQ₀ to column decoders CD₁₂₉-CD₀. Note that each of the 130 write routing control units WRCU₁₂₉-WRCU₀ is coupled to a corresponding one of the 130 column decoders CD₁₂₉-CD₀. Further note that there are two more column decoders (130) and write routing control units (130) than data lines DQ₁₂₇-DQ₀ (128). As described in more detail below, the two additional write routing control units and column decoders allow up to two defective memory block/column decoder pairs to be replaced. It is not necessary for the two defective memory block/column decoder pairs to be adjacent to one another.

Each of the write routing control units WRCU₁₂₉-WRCU₀ is coupled to receive three input data values. More specifically, each write routing control unit WRCU_(N) is coupled to receive a corresponding first data value DQ[N] from a corresponding data line DQ_(N), a second data value DQ[N−1] from a first previous data line DQ_(N−1) and a third data value DQ[N−2] from a second previous data line DQ_(N−2) (where 2≦N≦127). For example, write routing control unit WRCU₂ is coupled to receive data values DQ[2], DQ[1] and DQ[0]. Write routing control units WRCU₁₂₉ and WRCU₁₂₈ receive logic low (ground) input signals as illustrated because there are only 128 input data values (i.e., there are no data values DQ[129] or DQ[128]). Moreover, write routing control units WRCU₁ and WRCU₀ receive logic low (ground) input signals as illustrated because there is only one previous write routing control unit with respect to WRCU₁ (i.e., WRCU₀), and no previous write routing control units with respect to WRCU₀.

Write routing control units WRCU₁₂₇-WRCU₀ are further coupled to receive code signals C₁₂₈-C₁, respectively. These code signals C₁₂₈-C₁ have been described above in connection with read routing control units RRCU₁₂₇-RRCU₀. Write routing control units WRCU₁₂₉-WRCU₁₂₈ are coupled to receive code signal C₁₂₈.

In general, each of write routing control units WRCU₁₂₉-WRCU₀ routes one of its three corresponding data values as a corresponding output data value D[129:0] on data lines D₁₂₉-D₀. If memory blocks MB₁₂₇-MB₀ and column decoders CD₁₂₇-CD₀ are functional, then write routing control units WRCU₁₂₇-WRCU₀ are controlled to route data values DQ[127:0] to column decoders CD₁₂₇-CD₀, respectively.

If one of the memory block/column decoder pairs MB_(N)/CD_(N) is defective, then the write routing control units WRCU₁₂₈-WRCU_(N+1) are controlled to shift the data values DQ[127:N] one bit to the left in order to bypass the defective memory block/column decoder pair MB_(N)/CD_(N). For example, if memory block/column decoder pair MB₁/CD₁ is defective, then write routing control units WRCU₁₂₈-WRCU₂ are controlled to route the data values DQ[127:1], respectively, to column decoders CD₁₂₈-CD₂, respectively.

Similarly, if two of the memory block/column decoder pairs are defective, then the write routing control units are controlled to shift the data values two bits to the left in order to bypass the defective memory block/column decoder pairs. For example, if memory block/column decoder pairs MB₁/CD₁ and MB₀/CD₀ are defective, then write routing control units WRCU₁₂₉-WRCU₂ are controlled to route the data values DQ[127:0], respectively, to column decoders CD₁₂₉-CD₂, respectively.

FIG. 5 is a schematic diagram of write routing control unit WRCU₂ in accordance with one embodiment of the present invention. Write routing control units WRCU₁₂₉-WRCU₃ and WRCU₁-WRCU₀ are identical to write routing control unit WRCU₂ in the described embodiment. Write routing control unit WRCU₂ includes switches 501, 502 and 503, which are coupled to receive data signals DQ[0], DQ[1] and DQ[2], respectively. Switches 501-503 are controlled by code signal C[2:0], as illustrated. The code signal C[2:0] received by write routing control unit WRCU₂ is provided by the code signal C₂ generated by read routing control unit RRCU₁. As described above, code signal C₂ is a control signal that identifies whether none, one or both of the two previous memory block/column decoder pairs (MB₁/CD₁ and MB₀/CD₀) is defective. The generation of code signal C₂ is described above in connection with FIG. 3.

In general, if the two previous memory block/column decoder pairs MB₁/CD₁ and MB₀/CD₀ are functional, then the code signals C₂ provided to write routing control unit WRCU₂ are equal to [0,0,V_(DD)]. Under these conditions, code signal C₂ turns on switch 503, thereby routing data value DQ[2] to column decoder CD₂ as data signal D[2].

If one of the two previous memory block/column decoder pairs (MB₁/CD₁ and MB₀/CD₀) is defective, then the code signals C₂ provided to write routing control unit WRCU₂ are equal to [0,V_(DD),0]. Under these conditions, code signal C₂ turns on switch 502, thereby routing data value DQ[1] to column decoder CD₂ as data signal D[2]. This routing is appropriate because if one of the two previous memory block/column decoder pairs is defective, memory block MB₂ and column decoder CD₂ should process the data value DQ[1].

If both of the two previous memory block/column decoder pairs (MB₁/CD₁ and MB₀/CD₀) are defective, then the code signals C₂ provided to write routing control unit WRCU₂ are equal to [V_(DD),0,0]. Under these conditions, code signal C₂ turns on switch 501, thereby routing data value DQ[0] to column decoder CD₂ as data signal D[2]. This routing is appropriate because if both of the two previous memory block/column decoder pairs are defective, memory block MB₂ and column decoder CD₂ should process the data value DQ[0].

The remainder of the write routing control units operate in the same manner as write routing control unit WRCU₂. Consequently, up to two defective memory block/column decoder pairs can be replaced using redundant memory blocks MB₁₂₉-MB₁₂₈ and redundant column decoders CD₁₂₉-CD₁₂₈. At most, data values DQ[127:0] are shifted to the left by two write routing control units. As a result, the delays in transmitting data values DQ[127:0] to column decoders CD₁₂₉-CD₀ are approximately equal, even under worst case routing conditions. That is, no routing paths are significantly longer than any other routing paths, regardless of which memory block/column decoder pairs are defective.

One embodiment of the present invention provides a byte write masking circuit that enables a device that is accessing memory system 200 to specify a write operation of fewer than 128 bits. The 128-bit width of data bus DQ₁₂₇-DQ₀ is logically divided into sixteen 8-bit bytes. As described in more detail below, a byte write masking circuit is provided for enabling write operations to any selected set of these sixteen bytes.

FIG. 6 is a block diagram of a byte write masking circuit 600 in accordance with one embodiment of the present invention. Byte write masking circuit 600 is designed for use with memory system 200. As described above in connection with FIGS. 4 and 5, write data bits may be shifted by up to two bit locations to enable the replacement of defective memory block/column decoder pairs. Byte mask bits must therefore be similarly shifted to provide correspondence between the write data bits and the byte mask bits. As described below, byte write masking circuit 600 provides the appropriate shifting of the byte mask bits.

Byte write masking circuit 600 includes sixteen mask routing control units MRCU₁₅-MRCU₀. Each of mask routing control units MRCU₁₅-MRCU₀ is coupled to receive a pair of byte mask bits. More specifically, mask routing control units MRCU₁₅-MRCU₀ are coupled to receive corresponding byte mask bits BM[15:0], respectively. Each of the sixteen byte mask bits BM[15:0] corresponds with one of the sixteen 8-bit bytes provided on data lines DQ₁₂₇-DQ₀. In addition, mask routing control units MRCU₁₅-MRCU₁ are coupled to receive byte mask bits BM[14:0], respectively, from previous mask routing control units, and mask routing control unit MRCU₀ is coupled to receive a logic “0” byte mask bit (i.e., ground).

Each of mask routing control units MRCU₁₅-MRCU₀ is also coupled to receive a pair of code signals. Mask routing control units MRCU₁₅-MRCU₀ selectively route the byte mask bits BM[15:0] in response to the applied code signals, thereby providing byte mask input bits BMI[129:0]. Byte mask input bits BMI[129:0] are provided to enable terminals of column decoders CD₁₂₉-CD₀, respectively. A byte mask input bit having a logic low value enables the corresponding column decoder, such that write data is transmitted through the column decoder. Conversely, a byte mask input bit having a logic high value disables the corresponding column decoder, such that write data is prevented from passing through the column decoder.

In general, if none of memory blocks MB₁₂₇-MB₀ or column decoders CD₁₂₇-CD₀ is defective, then the byte mask bits BM[15:0] are routed directly through mask routing control units MRCU₁₅-MRCU₀, respectively. For example, byte mask bit BM[0] is routed through mask routing control unit MRCU₀ as byte mask input values BMI[7:0], byte mask bit BM[1] is routed through mask routing control unit MRCU₁ as byte mask input values BMI[15:8], and byte mask bit BM[15] is routed through mask routing control unit MRCU₁₅ as byte mask input values BMI[127:120].

If there is one defective memory block/column decoder pair located in mask routing control unit MRCU_(N), then each set of eight byte mask input values are shifted to the left by one bit location, beginning in mask routing control unit MRCU_(N+1). For example, if one of the memory block/column decoder pairs associated with mask routing control unit MRCU₀ is defective, then mask routing control unit MRCU₁ will route the byte mask bit BM[0] as byte mask input bit BMI[8]. As a result, the set of eight byte mask input values BMI[7:0] is effectively shifted one bit to the left. In this example, each of the other mask routing control units MRCU₁₅-MRCU₂ is controlled in a similar manner to provide one bit shift to the left. For example, mask routing control circuit MRCU₂ will route the byte mask bit BM[1] as byte mask input bit BMI[16], and mask routing control circuit MRCU₁₅ will route the byte mask bit BM[14] as byte mask input bit BMI[120].

If there are two defective memory block/column decoder pairs located to the right of mask routing control unit MRCU_(N), then each set of eight byte mask input values are shifted to the left by two bit locations, beginning in mask routing control unit MRCU_(N). For example, if two of the memory block/column decoder pairs associated with mask routing control unit MRCU₀ are defective, then mask routing control unit MRCU₁ will route the byte mask bit BM[0] as byte mask input bit BMI[8] and as byte mask input bit BMI[9]. As a result, the set of eight byte mask input values BMI[7:0] is effectively shifted two bits to the left. In this example, each of the other mask routing control units MRCU₁₅-MRCU₂ is controlled in a similar manner to provide a two bit shift to the left. For example, mask routing control circuit MRCU₂ will route the byte mask bit BM[1] as byte mask input bits BMI[16] and BMI[17], and mask routing control circuit MRCU₁₅ will route the byte mask bit BM[14] as byte mask input bits BMI[120] and BMI[121].

FIG. 7 is a schematic diagram of mask routing control unit MRCU₁ in accordance with one embodiment of the present invention. Mask routing control unit MRCU₁ includes switch circuits 701 and 702, which include switches 711-713 and 714-716, respectively. In the described embodiment, mask routing control units MRCU₁₅-MRCU₂ and MRCU₀ are identical mask routing control unit MRCU₁. (Note that within mask routing control unit MRCU₀, the switches corresponding to switches 701 and 702 will always route byte mask bit BM[0] as byte mask input bits BMI[1] and BMI[0]). FIG. 7 also illustrates read routing control units RRCU₉-RRCU₇ and write routing control units WRCU₉-WRCU₇.

As illustrated in FIG. 7, byte mask bit BM[1] is always routed to provide the six most significant byte mask input bits BMI[15:10]. The two least significant byte mask input bits BMI[9:8] are provided by switching circuits 701 and 702, respectively. Within switching circuit 701, switch 711 is connected to receive byte mask bit BM[0], while switches 712 and 713 are connected to receive byte mask bit BM[1]. Switches 711, 712 and 713 are controlled by the code signal C₉, which is provided by read routing control unit RRCU₈ in the manner described above in connection with FIGS. 2 and 3. Within switching circuit 702, switches 714 and 715 are connected to receive byte mask bit BM[0], while switch 716 is connected to receive byte mask bit BM[1]. Switches 714, 715 and 716 are controlled by the code signal C₈, which is provided by read routing control unit RRCU₇ in the manner described above in connection with FIGS. 2 and 3.

As described above, code signal C₈ will have a value of [0,0,V_(DD)] if all of memory blocks MB₇-MB₀ and column decoders CD₇-CD₀ are functional. In this case, byte mask bit BM[1] is routed through switch 716 as byte mask input bit BMI[8] (i.e., no shift is performed). This routing is appropriate because if none of memory blocks MB₇-MB₀ is defective, then the 8-bit data byte associated with memory blocks MB₇-MB₀ will actually be written to these memory blocks MB₇-MB₀.

Code signal C₈ will have a value of [0,V_(DD),0] if one of the memory block/column decoder pairs comprised by memory blocks MB₇-MB₀ and column decoders CD₇-CD₀ is defective. In this case, byte mask bit BM[0] is routed through switch 715 as byte mask input bit BMI[8]. In this case, a 1-bit shift is performed. This routing is appropriate because if only one of memory blocks MB₇-MB₀ is defective, then the 8-bit data byte that would normally be written to memory blocks MB₇-MB₀ will now be written to the seven non-defective memory blocks in the group of memory blocks MB₇-MB₀, plus memory block MB₈.

Finally, code signal C₈ will have a value of [V_(DD),0,0] if two of the memory block/column decoder pairs comprised by memory blocks MB₇-MB₀ and column decoders CD₇-CD₀ are defective. In this case, byte mask bit BM[0] is routed through switch 714 as byte mask input bit BMI[9]. As will become evident in view of the discussion of switch 701, this operation is part of a 2-bit shift.

Turning now to switch 701, code signal C₉ will have a value of [0,0,V_(DD)] if all of memory blocks MB₈-MB₀ and column decoders CD₈-CD₀ are functional. In this case, byte mask bit BM[1] is routed through switch 713 as byte mask input bit BMI[9] (i.e., no shift is performed). This routing is appropriate because if none of memory blocks MB₈-MB₀ is defective, then the 8-bit data byte associated with memory blocks MB₇-MB₀ will actually be written to these memory blocks MB₇-MB₀.

Code signal C₉ will have a value of [0,V_(DD),0] if one of the memory block/column decoder pairs comprised by memory blocks MB₈-MB₀ and column decoders CD₈-CD₀ is defective. In this case, byte mask bit BM[1] is routed through switch 712 as byte mask input bit BMI[9] (i.e., no shift is performed). This routing is appropriate because if only one of memory blocks MB₈-MB₀ is defective, then the 8-bit data byte that would normally be written to memory blocks MB₇-MB₀ will now be written to the eight non-defective memory blocks in the group of memory blocks MB₈-MB₀.

Finally, code signal C₉ will have a value of [V_(DD),0,0] if two of the memory block/column decoder pairs comprised by memory blocks MB₈-MB₀ and column decoders CD₈-CD₀ are defective. In this case, byte mask bit BM[0] is routed through switch 711 as byte mask input bit BMI[9] (i.e., a 2-bit shift is performed). This routing is appropriate because if two of memory blocks MB₈-MB₀ are defective, then the 8-bit data byte that would normally be written to memory blocks MB₇-MB₀ will now be written to the eight non-defective memory blocks in the group of memory blocks MB₉-MB₀.

In another embodiment of the present invention, the above-described circuitry is modified to provide bank enable signals to a plurality of memory banks.

FIG. 8 is a block diagram of a memory system 800 that includes plurality of memory banks BANK₁₉-BANK₀. These memory banks BANK₁₉-BANK₀ are enabled (and disabled) by bank enable signals BEN[19]-BEN[0], respectively. A logic high bank enable signal enables the corresponding bank, and a logic low bank enable signal disables the corresponding bank.

Bank enable signals BEN[19]-BEN[0] are provided by bank routing control units BRCU₁₉-BRCU₀, respectively. Each of bank routing control units BRCU_(N) is coupled to receive bank enable signals B[N], B[N−1] and B[N−2], where N is greater than 1. Bank routing control unit BRCU₁ is coupled to receive bank enable signals B[1], B[0] and a logic ‘0’ signal. Bank routing control unit BRCU₀ is coupled to receive bank enable signal B[0] and a pair of logic ‘0’ signals. Each of bank routing control units BRCU₁₉-BRCU₀ is controlled to route one of its three input signals as a corresponding bank enable signal BEN₁₉-BEN₀ in response to an applied code signal C_(i)[2:0].

FIG. 9 is a schematic diagram of bank routing control unit BRCU₂ in accordance with one embodiment of the present invention. In the described embodiment, bank routing control units BRCU₁₉-BRCU₃ and BRCU₁-BRCU₀ are identical to bank routing control unit BRCU₂. Bank routing control unit BRCU₂ includes inverters 301-305, p-channel transistor 307, n-channel transistor 308, fuse 309 and switches 311-312. These elements were previously described in connection with FIG. 3, and will therefore not be described in detail again. In general, fuse 309 is blown if the corresponding bank BANK₂ is defective, and is not blown if the corresponding bank BANK₂ is functional. At start-up, the reset signal RST is initially asserted high and then de-asserted low. If bank BANK₂ is functional, then inverter 304 will provide a logic high GOOD control signal that closes switch 311. Conversely, if bank BANK₂ is defective, then inverter 305 will provide a logic high GOOD# control signal that closes switch 312. Switches 311 and 312 pass the applied code signal C₂ in the manner described above in connection with FIG. 3. (Note that bank routing control unit BRCU₀ receives an initial code signal C₀ having a value of [0,0,V_(DD)].)

The GOOD control signal is also applied to an input terminal of AND gate 903. The other input terminals of AND gate 903 are coupled to receive the code signal C_(O)[2:0]. If the GOOD control signal has a logic high value (i.e., BANK₂ is functional), then the output code signals C_(O)[2:0] are routed through AND gate 903 to control switches 900-902, respectively. As described above, the code signals C_(O)[2:0] will have a value of [0,0,V_(DD)] if none of the memory banks BANK₂-BANK₀ is defective, a value of [0,V_(DD),0] if one of the memory banks BANK₂-BANK₀ is defective, and a value of [V_(DD),0,0] if two of the memory banks BANK₂-BANK₀ are defective. Accordingly, if none of the memory banks BANK₂-BANK₀ is defective, then switch 900 is enabled, thereby routing bank enable signal B[2] to bank BANK₂ as the bank enable signal BEN[2]. If one of the memory banks BANK₂-BANK₀ is defective, then switch 901 is enabled, thereby routing bank enable signal B[1] to bank BANK₂ as the bank enable signal BEN[2]. Finally, if two of the memory banks BANK₂-BANK₀ are defective, then switch 902 is enabled, thereby routing bank enable signal B[0] to bank BANK₂ as the bank enable signal BEN[2]. In this manner, the bank enable signals are appropriately shifted to avoid defective memory banks. Advantageously, the delays in routing the bank enable signals to the memory banks are substantially equivalent, regardless of which of the memory banks may be defective.

If memory bank BANK₂ itself is defective, then the GOOD control signal will have a logic low value, thereby causing AND gate 903 to provide logic low signals to disable all of switches 900-902. Under these conditions, the GOOD# control signal has a logic high value, which is provided to the gate of n-channel transistor 904, thereby turning on this transistor. Turned on transistor 904 couples the output terminal of bank routing control unit BRCU₂ to ground, thereby providing a logic low bank enable signal BEN[2]. Defective bank BANK₂ is thereby disabled.

Alternative Embodiment

FIG. 10A is a block diagram of a memory system 1000 that implements a read and write redundancy scheme in accordance with another embodiment of the present invention. Similar elements in memory system 1000 and memory system 200 (FIG. 2) are labeled with similar reference numbers. Thus, memory system 1000 includes memory blocks MB₁₂₉-MB₀ and column decoders CD₁₂₉-CD₀. Memory system 1000 also includes read/write routing control units RU₁₂₇-RU₀, external data lines DQ₁₂₇-DQ₀, internal data lines D₁₂₉-D₀ and routing unit programmer 1300. In the described embodiment, column decoders CD₁₂₉-CD₀ include read-write circuitry, such as read data amplifiers and write drivers, thereby providing an interface between data lines D₁₂₉-D₀ and memory blocks MB₁₂₉-MB₀.

Each of the 128 read/write routing control units RU₁₂₇-RU₀ is coupled to a corresponding one of the 128 data lines DQ₁₂₇-DQ₀. Each of the 128 read/write routing control units RU₁₂₇-RU₀ is also coupled to a corresponding trio of consecutive column decoders CD₁₂₉-CD₀ (i.e., a corresponding trio of consecutive data lines D₁₂₉-D₀). More specifically, read/write routing control unit RU_(n) is coupled to column decoders CD_(n), CD_(n+1), and CD_(n+2) (or data lines D_(n), D_(n+1) and D_(n+2)), where n is an integer between 0 and 127. As described in more detail below, each read/write routing control unit RU_(n) selectively couples one of its corresponding trio of column decoders CD_(n), CD_(n+1) CD_(n+2) to its corresponding data line DQ_(n) under the control of routing unit programmer 1200. In the described embodiment, routing units RU₁₂₇-RU₀ pass signals in a bi-directional manner between data lines D₁₂₉-D₀ and data lines DQ₁₂₇-DQ₀. The data values present on data lines DQ₁₂₇-DQ₀ are labeled as data values DQ[127:0], respectively. The data values present on data lines D₁₂₉-D₀ are labeled as data values D[129:0], respectively.

Although the present embodiment is described in connection with a single row of memory block/column decoder pairs, it is understood that in other embodiments, multiple rows of memory block/column decoder pairs can be used. FIG. 10B illustrates a memory system 1000B having three rows of memory block/column decoder pairs. In addition to memory blocks MB₁₂₉-MB₀ and column decoders CD₁₂₉-CD₀, memory system 1000B includes memory blocks MB′₁₂₉-MB′₀, column decoders CD′₁₂₉-CD′₀, memory blocks MB″₁₂₉-MB″₀ and column decoders CD′₁₂₉-CD′₀. Within each column, the column decoders are connected to a global bit line. Each global bit line is coupled to a read data amplifier and a write driver circuit (not shown). The read amplifier and write driver circuit are coupled to the routing units.

Thus, the output terminals of column decoders CD″₂, CD′₂ and CD₂ are commonly connected to a global bit line (i.e., line D₂). If a defect exists in any one of the memory blocks or column decoders in a column, then the entire column can be replaced by configuring the routing units in the manner described in more detail below. For example, if there is a defect in any one of memory blocks MB″₂, MB′₂, MB₂ or column decoders CD″₂, CD′₂ and CD₂, then all of these elements can be replaced by coupling routing unit RU₂ to memory blocks MB″₃, MB′₃, MB₃ and column decoders CD″₃, CD′₃ and CD₃. In other embodiments, larger numbers of rows (e.g., 32 rows) of memory block/column decoder pairs can be used, thereby minimizing the percentage of layout area consumed by routing units RU₁₂₇-RU₀ and routing unit programmer 1200.

As described above, there are two more memory block/column decoder pairs than routing control units. The two additional memory block/column decoder pairs allow up to two defective memory block/column decoder pairs to be replaced. Although the present embodiment describes a scheme having two possible redundancies, more or less redundancy can be easily incorporated with minor modification to the present embodiment.

Construct of Routing Units

FIG. 11 is a circuit diagram of a read/write routing control unit RU_(n) in accordance with one embodiment of the present invention. Routing unit RU_(n) includes router circuit 1101 and router controller 1102. Router circuit 1101 includes three transmission gates 1111, 1112 and 1113, which connect data lines D_(n), D_(n+1) and D_(n+2), respectively, to data line DQ_(n). Inverters 1121-1123 are coupled to transmission gates 1111-1113, respectively, as illustrated. Transmission gates 1111, 1112 and 1113 are controlled by select signals SEL0, SEL1 and SEL2, respectively, which are generated by router controller 1102.

Router controller 1102 includes D-Q flip-flops 1131-1132 and logical NOR gate 1141. The D input terminal of flip-flop 1131 is connected to receive the shift input signal S_(n) at the shift input terminal S_(I). The Q output terminal of flip-flop 1131 provides the SEL2 signal to transmission gate 1113, to NOR gate 1141, and to the D input terminal of flip-flop 1132. The Q output terminal of flip-flop 1132 provides the SEL1 signal to transmission gate 1112, to NOR gate 1141, and to the S_(O) output terminal of routing unit RU_(n). NOR gate 1141 provides the SEL0 signal to transmission gate 1111 in response to the SEL1 and SEL2 signals. The clock input terminals of flip-flops 1131 and 1132 are coupled to receive a scan clock signal (SCK) provided by routing unit programmer 1300.

As described in more detail below, flip-flops 1131-1132 will be programmed to store configuration values “10”, “01” or “00” (configuration values “11” are not allowed). Table 1 below summarizes the states of the SEL0-SEL2 signals for the various configuration values stored in flip-flops 1131-1132. Note that in Table 1, the configuration values stored in flip-flops 1131 and 1132 are identified as D₁₁₃₁ and D₁₁₃₂, respectively.

TABLE 1 D₁₁₃₁ D₁₁₃₂ SEL2 SEL1 SEL0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0

When the SEL0 signal is high, transmission gate 1111 is conducting (turned on), and transmission gates 1112 and 1113 are non-conducting (turned off). As a result, data line D_(n) is connected to data line DQ_(n).

When the SEL1 signal is high, transmission gate 1113 is turned on, and transmission gates 1111 and 1113 are turned off. As a result, data line D_(n+1) is connected to data line DQ_(n).

When the SEL2 signal is high, transmission gate 1113 is turned on, and transmission gates 1111 and 1112 are turned off. As a result, data line D_(n+2) is connected to data line DQ_(n).

Flip-flops 1131-1132 are serially connected to form a shifter circuit 1103. Thus, a value shifted into flip flop 1131 during one cycle of the SCK signal is shifted into flip flop 1132 during a subsequent cycle of the SCK signal. The input terminal S_(I) of shifter circuit 1103 connected to the output terminal S_(O) of the shifter circuit in the left-adjacent routing unit RU_(n+1). Similarly, the output terminal S_(O) of shifter circuit 1103 is connected to the input terminal SI of the shifter circuit in the right-adjacent routing unit RU_(n−1). As a result, a 256-bit shift-chain circuit extending through routing units RU₁₂₇-RU₀ is formed. As illustrated in FIG. 10A, the S_(I) input terminal of the shifter circuit in routing unit RU₁₂₇ is connected to receive the SIN signal provided by routing unit programmer 1300. As described in more detail below, routing unit programmer 1300 provides the data values to be shifted into routing units RU₁₂₇-RU₀ according to the defective/non-defective status of memory blocks MB₁₂₉-MB₀.

Repair Process

In the default mode, when none of memory blocks MB₁₂₇-MB₀ or column decoders CD₁₂₇-CD₀ is defective, routing units RU₁₂₇-RU₀ are configured such that data lines D₁₂₇-D₀ are connected to data lines DQ₁₂₇-DQ₀, respectively. As a result, the data signals D[127:0] are connected through routing units RU₁₂₇-RU₀ as data signals DQ[127:0]. That is, each of routing units RU₁₂₇-RU₀ passes the signal on its ‘right’ (A) terminal. In this case, the redundant memory blocks MB₁₂₉-MB₁₂₈ and redundant column decoders CD₁₂₉-CD₁₂₈ are not connected to any of data lines DQ[127:0].

If one memory block/column decoder pair is defective, then routing units RU₁₂₇-RU₀ are programmed to isolate the defective pair from data lines DQ₁₂₇-DQ₀. For example, if memory block MB_(n), where n can be any number in the range of 0 to 127, is defective, then routing unit RU_(n) is configured to connect data line D_(n+1) to data line DQ_(n). In addition, routing units RU₁₂₇-RU_(n+1) are programmed to connect data lines D₁₂₈-D_(n+2) to data lines DQ₁₂₇-DQ_(n+1), respectively. In other words, each of routing units RU₁₂₇-RU_(n) is configured to pass the signals on its ‘middle’ (B) terminal, while each of routing units RU_(n−1)-R₀ is configured to pass the signal on its ‘right’ (A) terminal. Stated another way, the routing position of each of routing units RU₁₂₇-RU_(n) is shifted to the left by one position with respect to the default position.

To accomplish the routing described above, the shifter circuits 1103 in routing units RU₁₂₇ to RU_(n) are programmed with a configuration value of “01”, and the shifter circuits 1103 in routing units RU_(n−1) to RU₀ are programmed with a configuration value of “00”.

Assume that an additional memory block MB_(m) or column decoder CD_(m) is defective, where m is any number in the range of n+1 to 127. In this case, routing units RU₁₂₇-RU_(m−1) are programmed to connect data lines D₁₂₉-D_(m+1) to data lines DQ₁₂₇-DQ_(m−1), respectively. That is, each of routing units RU₁₂₇-RU_(m−1) is configured to pass the signal on its ‘left’ (C) terminal.

Routing units RU_(m−2)-RU_(n) are programmed to connect data lines D_(m−1)-D_(n+1) to data lines DQ_(m−2)-DQ_(n). That is, each of routing units RU_(m−2) to RU_(n) is configured to pass the signal on its ‘middle’ (B) terminal.

Routing units RU_(n−1) to RU₀ are programmed to connect data lines D_(n−1) to D₀ to data lines DQ_(n−1) to DQ₀. That is, each of routing units RU_(n−1) to RU₀ is configured to pass the signal on its ‘right’ (A) terminal.

Stated another way, the routing position of each of routing units RU₁₂₇-RU_(m−1) is shifted to the left by two positions with respect to the default position, the routing position of each of routing units RU_(m−2)-RU_(n) is shifted to the left by one position with respect to the default position, and each of the routing units RU_(n−1)-RU₀ is not shifted with respect to the default position.

To accomplish the routing described above, the shifter circuits 1103 in routing units RU₁₂₇ to RU_(m−1) are programmed with a configuration value of “10”, the shifter circuits. 1103 in routing units RU_(m−2) to RU_(n) are programmed with a configuration value of “01”, and the shifter circuits 1103 in routing units RU_(n−1) to RU₀ are programmed with a configuration value of “00”.

Scheme for More than Two Redundant Memory Blocks

The routing unit RU_(n) of FIG. 11 can be readily modified for use in systems having a larger number of redundant elements. FIG. 12 is a circuit diagram of a routing unit RU_(n) that is used in a system having three redundant memory block/column decoder pairs. Because the routing unit RU_(n) of FIG. 12 is similar to the routing unit RU_(n) of FIG. 11, similar elements are labeled with similar reference numbers in FIGS. 11 and 12. The routing unit RU_(n) of FIG. 12 includes a router 1201 and a router controller 1202. Router 1201 includes four transmission gates 1111-1114 and four corresponding inverters 1121-1124. Transmission gates 1111, 1112, 1113 and 1114 are controlled by select signals SEL0, SEL1, SEL2 and SEL3, respectively. Router 1201 connects one of data lines D_(n+3)-D_(n) to data line DQ_(n) in response to the SEL[3:0] signals. Select signals SEL[3:0] are generated by logic gates 1141-1144 in response to the contents of flip-flops 1131 and 1132. Select signal SEL3 is generated using logical AND gate 1144, which has input terminals coupled to the Q output terminals of flip-flops 1131 and 1132. Select signal SEL2 is generated using logical NOR gate 1143, which has an inverting input terminal coupled to the Q output terminal of flip-flop 1131, and a non-inverting input terminal coupled to the Q output terminal of flip-flop 1132. Select signal SEL1 is generated using logical NOR gate 1142, which has a non-inverting input terminal coupled to the Q output terminal of flip-flop 1131, and an inverting input terminal coupled to the Q output terminal of flip-flop 1132. SEL1 and SEL2 signals. Select signal SEL0 is generated using logical NOR gate 1141, which is described above in connection with FIG. 11. Shifting circuit 1103 does not change in the embodiment of FIG. 12.

Table 2 below summarizes the states of the SEL[3:0] select signals for the various configuration values stored in flip-flops 1131-1132. Note that in Table 2, the configuration values stored in flip-flops 1131 and 1132 are identified as D₁₁₃₁, and D₁₁₃₂, respectively.

TABLE 2 D₁₁₃₁ D₁₁₃₂ SEL3 SEL2 SEL1 SEL0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0

The routing unit RU_(n) of FIG. 12 operates as follows to replace three defective memory blocks MB_(p), MB_(m) and MB_(n), where n is less than m, and m is less than p. Shifters in routing units RU_(p−2) and above are programmed with the value “11”, shifters in routing units RU_(p−3) to RU_(m−1) are programmed with the value “10”, shifters in routing units RU_(m−2) to RU_(n) are programmed with the value “01”, and shifters in routing units RU_(n−1) to RU₀ are programmed with the value of 00.

In general, for a system having k redundant memory blocks, the routing unit will include a router having “k” positions controlled by a shifter of “i” bits, where k equals to 2 to the power i (i.e., k=2^(i)). The shifter circuits of the routing units are connected to form a shift chain so that the flip flops in the shifter circuits can be programmed serially with a value of “j”, where j has a value between 0 to k−1, assuming that the shifter has a default routing position of 0. To repair k defective memory blocks, shifters in routing units RU_(x−j−1) to RU_(y−p), between two defective memory blocks with locations x and y (x>y) are programmed with the value j, where j and p equal the number of defective blocks having an address less than x and y respectively.

For example, assume that there are seven redundant memory blocks (i.e., k=7), and seven defective memory blocks at locations 110, 100, 90, 80, 25, 10 and 4. Further assume that each of routing unit RU₁₂₇-RU₀ is able to shift by seven, six, five, four, three, two, one or zero locations in response to programmed j values of “111”, “110”, “101”, “100”, “011”, “010”, “001” and “000”, respectively. In accordance with the equations above, the routing units RU₁₂₇-RU₀ are programmed to store j values according to Table 3 below.

TABLE 3 J Value Stored in Routing Units 000 RU₃-RU₀ 001 RU₈-RU₄ 010 RU₂₂-RU₉  011 RU₇₆-RU₂₃ 100 RU₈₅-RU₇₇ 101 RU₉₄-RU₈₆ 110 RU₁₀₃-RU₉₅  111 RU₁₂₇-RU₁₀₄

The routing units corresponding with a given j value are determined as set forth in the following example, which determines the routing units that receive the value of j=“100” (i.e., binary “four” ). In the present example, the defective memory block at location 90 has exactly four defective memory blocks at lower addresses. Thus, x=90 in the present example. The next (right-adjacent) defective memory block is present at location 80, and has exactly three defective memory blocks at lower addresses. Thus, y=80 and p=3 in the present example. As described above, the routing units storing a particular j value are defined by RU_(x−j−1) to RU_(y−p). In the present example, this becomes RU⁽⁹⁰⁻⁴⁻¹⁾ to RU⁽⁸⁰⁻³⁾, or RU₈₅ to RU₇₇, which corresponds with the fifth entry of Table 3.

Shift-chain Programming

FIG. 13 is a block diagram of routing unit programmer 1300 for programming the shift chain of routing units RU₁₂₇-RU₀ in accordance with one embodiment of the present invention. Routing unit programmer 1300 generates a configuration data input signal CIN, which is provided to routing unit RU₁₂₇ as the shift input signal S₁₂₇. This input signal CIN is sequentially shifted into the other routing units RU₁₂₆-RU₀. The propagation of the configuration data in the shift-chain is controlled by the shift clock signal SCK, which is also generated by routing unit programmer 1300. Routing unit programmer 1300 includes configuration data generator 1301 and sequencer 1302.

Configuration data generator 1301 includes comparators 1311-1312, non-volatile storage elements 1313-1316, OR gate 1320 and flip-flops 1321-1322. Non-volatile storage elements 1313-1316 can be constructed using, for example, fuses, anti-fuses, or EEPROM cells. Non-volatile storage elements 1313 and 1315 store first and second redundancy enable bits, respectively, which are used to enable or disable comparators 1311 and 1312, respectively. Non-volatile storage element 1314 stores the address of a first defective memory block. Non-volatile storage element 1316 stores an address which is one less than the address of a second defective memory block. For example, if memory blocks MB_(m) and MB_(n) are defective (where n is smaller than m), then non-volatile storage element 1314 is programmed with a value of n and non-volatile storage element 1316 is programmed with a value of m−1. The contents of storage elements 1314 and 1316 are provided to comparators 1311 and 1312, respectively.

Comparators 1311 and 1312 are also coupled to receive an address signal A[6:0] from modulo-128 counter 1331. When enabled, comparator 1311 provides a logic high HIT1 signal to the RESET terminal of flip flop 1322 when the contents of storage element 1314 match the address signal A[6:0]. Similarly, when enabled, comparator 1312 provides a logic high HIT2 signal to the SET terminal of flip flop 1321 and to an input terminal of OR gate 1320 when the contents of storage element 1316 match the address signal A[6:0]. A RESET signal is provided to OR gate 1320 and the RESET terminal of flip flop 1321. The output terminal of OR gate 1320 provides an R1 signal to the RESET input terminal of flip flop 1322. Flip-flops 1321 and 1322 are connected to form a circular queue, with the Q output terminal of flip flop 1321 connected to the D input terminal of flip flop 1322, and the Q output terminal of flip flop 1322 connected to the D input terminal of flip flop 1321. The circular queue stores a two-bit configuration value for programming two-bit shifter circuit 1103 in routing unit RU_(n) (FIG. 11). As described in more detail below, the two-bit configuration value stored in flip flops 1321-1322 is controlled by the RESET signal, the HIT1 and HIT2 signals. Flip flops 1321 and 1322 are clocked by a system clock signal, CLK. However, flip flops 1321 and 1322 can be asynchronously set or reset through their RESET and SET input terminals. The Q output terminal of flip flop 1322 provides the CIN signal.

Sequencer 1302 includes modulo-128 counter 1331, prescalar circuit 1332, RS flip-flop 1333 and AND gate 1334. Modulo-128 counter 1331, prescalar circuit 1332 and the SET terminal of RS flip-flop 1333 are coupled to receive the RESET signal. Prescalar circuit 1332 receives the system clock signal CLK, and in response provides a divided clock signal to modulo-128 counter 1331. In response, modulo-128 counter provides a 7-bit address signal A[6:0] and a FULL signal, which is asserted high when the A[6:0] signal has all logic “1” values. The FULL signal is provided to the RESET terminal of flip flop 1333. The Q output terminal of flip flop 1333 is provided to an input terminal of AND gate 1334. The SCK signal is provided at the output terminal of AND gate 1334. The SCK signal is enabled by the Q output signal of R-S flip-flop 1333, which is driven high when the RESET signal is asserted high, and is driven low when a full-count is reached in the modulo-128 counter.

Address signal A[6:0] identifies the location of the routing unit on the shift chain to which the configuration input signal CIN is to be transmitted. A modulo-128 counter is required because there are 128 routing units RU₁₂₇-RU₀ used in the present embodiment. Because each routing unit RU_(n) includes a 2-bit shifter circuit 1103, prescalar circuit 1332 divides the system clock signal CLK by two in order to distinguish the two locations in each shifter circuit 1103.

Circuit 1300 operates as follows. In the present example, there are two defective memory blocks MB_(m) and MB_(n) (m>n). Thus, storage elements 1313 and 1315 are programmed to store logic low values, thereby enabling comparators 1311 and 1312. Storage elements 1314 and 1316 are programmed to store the values n and m−1, respectively. At the beginning of the programming operation, the RESET signal is driven high, thereby resetting outputs of modulo-128 counter 1331, prescalar circuit 1332, and flip flops 1321-1322 to logic “0” values. However, R-S flip-flop 1333 is set to provide a logic high output signal in response to the logic high RESET signal. The high output signal provided by flip-flop 1333 enables the SCK signal to be generated in response to the CLK signal. Modulo-128 counter 1331 increments address signal A[6:0] once every two cycles of the CLK signal.

Before address signal A[6:0] reaches n, the HIT1, HIT2, RESET and R1 signals are all driven low. Consequently, output of flip flops 1321-1322 remain at logic “0” values. Shifter circuits 1103 in routing units RU_(n−1)-RU₀ will thereby be programmed to store a value of “00”. When address A[6:0] is equal to n, comparator 1311 drives the HIT1 signal to a logic high state, but comparator 1312 continues to drive the HIT2 signal to a logic low state. The high state of the HIT1 signal sets the output signal of flip flop 1322 to a logic high state. As a result, the circular queue is loaded with the value “01”. Starting from address n, the shifter circuits 1103 at addresses n and greater are programmed to store a configuration value of “01”. This continues until address signal A[6:0] reaches a count of m−1. At this time, comparator 1312 drives the HIT2 signal to a logic high state. Note that when address signal A[6:0] is equal to n, the HIT1 signal is driven low. The high state of the HIT2 signal causes the R1 signal to be driven high by OR gate 1320. The high states of the HIT2 and R1 signals changes the output signals of flip flops 1321 and 1322 to “1” and “0”, respectively. As a result, shifter circuits 1103 in routing units RU₁₂₇ to RU_(m−1), are programmed to store a configuration value of “10”.

When modulo-128 counter 1331 reaches its full count of 127, the FULL output signal is driven high, thereby resetting the output of R-S flip-flop 1333 to a logic low state, which in turn drives the shift clock signal SCK low, terminating the routing unit programming operation. The SCK signal remains low until the RESET signal is asserted high.

If there is only one defective memory block, then storage element 1315 is programmed with a logic high value, thereby disabling comparator 1312.

If there are no defective memory blocks, then storage elements 1313 and 1315 are both programmed with a logic high value, thereby disabling both of comparators 1311 and 1312.

Although the described routing unit programmer 1300 provides configuration values for a memory system having two redundant memory blocks, routing unit programmer 1300 can be easily modified by one skilled in the art to provide configuration values for memory systems having any other number of redundant memory blocks in view of the above disclosure.

Separate Read and Write Data Path

The redundancy scheme described above can be easily extended to memory systems having separate read and write data paths. FIG. 14 is a circuit diagram of a routing unit RU_(x) for separately routing read and write data from and to a set of memory blocks. Routing unit RU_(x) is similar to routing unit RU_(n) of FIG. 11. In the embodiment of FIG. 14, the internal data bus is separated into a set of read data lines RD₁₂₉-RD₀ and a set of write data lines WD₁₂₉-WD₀. The routing units couple the set of read data lines RD₁₂₉-RD₀ to a set of read data lines RDQ₁₂₇-RDQ₀. Similarly, the routing units couple the set of write data lines WD₁₂₉-WD₀ to a set of write data lines WDQ₁₂₇-WDQ₀. Routing unit RU_(x) is coupled to read data lines RDQ_(x), read data lines RD_(x+2), RD_(x+1), and RD_(x), write data lines WDQ_(x) and write data lines WD_(x+2), WD_(x+1) and WD_(x). Routing unit RU_(x) includes a first set of transmission gates 1401-1403 and inverters 1411-1413 which provides a connection between one of the write data lines WD_(x+2), WD_(x+1) and WD_(x) and the write data line WDQ_(x). Routing unit RU_(x) similarly includes a second set of transmission gates 1404-1406 and inverters 1414-1416 which provides a connection between one of the read data lines RD_(x+2), RD_(x+1) and RD_(x) and the read data line RDQ_(x). Routing unit RU_(x) uses a shifter circuit 1403 that is identical to the above-described shifter circuit 1103 (FIG. 11). Thus, shifter circuit 1403 includes a pair of flip flops 1431-1432 that are connected in the same manner as flip flops 1131-1132 (FIG. 11). Routing unit RU_(x) also includes a NOR gate 1441 that is connected in a manner similar to NOR gate 1141 (FIG. 11).

Transmission gates 1401-1403 are controlled to function as a 3-to-1 de-multiplexer that routes a write data value from the write data line WDQx to one of the write data lines WD_(x+2), WD_(x+1) and WD_(x). Transmission gates 1404-1406 are controlled to function as a 3-to-1 multiplexer that routes a read data value from one of the read data lines RD_(x+2), RD_(x+1) and RD_(x) to the read data line RDQx. The multiplexing and de-multiplexing of the read and write data signals are controlled by select signals SEL2, SEL1 and SEL0. Routing unit RU_(x) is programmed in the same manner as described above for routing unit RU_(n) (FIGS. 11-13.)

The present invention can also be extended to implement a memory system with write masking. FIG. 15 is a circuit diagram of a routing unit RU_(x) for separately routing write data and write masking information (the read data routing path is not shown in FIG. 15 for purposes of clarity.) Similar elements in FIGS. 14 and 15 are labeled with similar reference numbers. Thus, the routing unit RU_(x) of FIG. 15 includes transmission gates 1401-1403 and inverters 1411-1413, which provide a connection between one of the write data lines WD_(x+2), WD_(x+1) and WD_(x) and the write data line WDQ_(x). Routing unit RU_(x) of FIG. 15 also includes flip flops 1431-1432 and NOR gate 1441.

In addition, routing unit RU_(x) of FIG. 15 includes transmission gates 1407-1409 and inverters 1417-1419, which provide a connection between one of the write mask lines WM_(x+2), WM_(x+1) and WM_(x) and the write mask line WMQ_(x). Transmission gates 1407-1409 are configured to operate in the same manner as transmission gates 1401-1403. Thus, if write data value WDQ_(x) is routed on one of write data lines WD_(x+2), WD_(x+1) or WD_(x), then write mask signal WMQ_(x) is routed on a corresponding one of write mask lines WM_(x+2), WM_(x+1) or WM_(x), respectively.

Write data line WD_(x) and write mask line WM_(x) are coupled to input and enable terminals, respectively, of a write driver 1501 in column decoder CD_(x). Similarly, write data line WD_(x+1) and write mask line WM_(x+1) are coupled to input and enable terminals, respectively, of a write driver 1502 in column decoder CD_(x+1). Finally, line WD_(x+2) and write mask line WM_(x+2) are coupled to input and enable terminals, respectively, of a write driver 1503 in column decoder CD_(x+2). In this manner, the write masking information is transmitted with the write data.

Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications which would be apparent to a person skilled in the art. For example, although the invention has been described in connection with two redundant memory blocks, it is understood that the invention can be modified to include other numbers of redundant memory blocks (e.g., 1 or 3). Furthermore, although the routing units have been described as being loaded from a single shift chain, it is understood that multiple shift chains can be used to load configuration data into the routing units. In addition, it is understood that many types of memory blocks can be used in connection with the redundancy scheme of the present invention, including, but not limited to, DRAM, SRAM, EPROM, EEPROM and Flash EPROM. Moreover, although the redundancy scheme was described in connection with memory blocks, it is understood that the principles of the present invention can be applied to types of circuit blocks. Thus, the invention is limited only by the following claims. 

What is claimed is:
 1. A redundancy system comprising: a plurality of circuit blocks; a plurality of routing units configured to route read and write data between the circuit blocks and a data bus, wherein at least one shifter circuit extends through the routing units, the shifter circuit storing values for configuring the routing units; and a routing unit programmer for loading the shifter circuit through a routing unit.
 2. The redundancy system of claim 1, wherein the shifter circuit comprises one or more series connected storage elements in each routing unit.
 3. The redundancy system of claim 1, wherein each of the routing units includes a router coupled between a predetermined number of the circuit blocks and the data bus.
 4. The redundancy system or claim 3, wherein each router is controlled by one or more values stored in the shifter circuit.
 5. The redundancy system of claim 3, wherein each of the routers is configured to connect one of the circuit blocks to the data bus.
 6. The redundancy system of claim 3, wherein the predetermined number is two or greater.
 7. The redundancy system of claim 3, wherein each router includes a plurality of transmission gates coupled in parallel to the data bus.
 8. The redundancy system of claim 3, wherein the predetermined number of circuit blocks are consecutive circuit blocks.
 9. The redundancy system of claim 1, wherein the data bus includes a plurality of data lines used to transmit both read data and write data.
 10. The redundancy system of claim 1, wherein the data bus includes a first set of data lines for carrying read data, and a second set of data lines for carrying write data.
 11. The redundancy system of claim 1, wherein the routing unit programmer comprises: a first register for storing a first address associated with a first defective circuit block; a counter for sequentially providing addresses associated with all of the circuit blocks; and a first comparator coupled to the counter and the first register.
 12. The redundancy system of claim 11, further comprising a first sequential logic element coupled to an output of the first comparator, wherein the shifter circuit is loaded through the first sequential logic element.
 13. The redundancy system of claim 11, further comprising: a second register for storing a second address associated with a second defective circuit block; and a second comparator coupled to the counter and the second register.
 14. The redundancy system of claim 13, further comprising: a first sequential logic element coupled to an output of the first comparator, a second sequential logic element coupled to an output terminal of the second comparator, wherein the first and second sequential logic elements are connected in a circular queue.
 15. The redundancy system of claim 14, wherein the shifter circuit is loaded with valves from the first and second sequential logic elements.
 16. A method of replacing defective circuit blocks with redundant circuit blocks, the method comprising the steps of: identifying a first address of a first defective circuit block; identifying a second address of a second defective circuit block; serially loading values into a shifter circuit, wherein the values are selected in response to the first address response to the first address and the second address; bypassing the first defective circuit block and the second defective circuit block in response to values stored in the shifter circuit; and connecting a first redundant circuit block in response to values stored in the shifter circuit; connecting a first redundant circuit block and a second redundant circuit block in response to values stored in the shifter circuit.
 17. The method of claim 16, further comprising the steps of: shifting connections to one or more circuit blocks located between the second defective circuit block and the first defective circuit block by one position in response to values stored in the shifter circuit; and shifting connections to one or more circuit blocks located between the first and second redundant circuit blocks and the second defective circuit block by two positions in response to values stored in the shifter circuit.
 18. The method of claim 16, wherein the step of serially loading values into the shifter circuit comprises the steps of: storing the first address in a first register; storing the second address minus one in a second register; sequentially comparing the first address and the second address minus one with addresses associated with a set of circuit blocks; loading a value into the shifter circuit; modifying the value loaded into the shifter circuit when the first address matches an address associated with a circuit block in the set of circuit blocks; and modifying the value loaded into the shifter circuit when the second address minus one matches an address associated with a circuit block in the set of circuit blocks.
 19. A method of replacing defective circuit blocks with redundant circuit blocks, the method comprising the steps of: identifying a first address of a first defective circuit block; serially loading values into a shifter circuit, wherein the values are selected in response to the first address, wherein the step of serially loading values into the shifter circuit comprises the steps of: storing the first address in a first register; sequentially comparing the first address with addresses associated with a set of circuit blocks; loading a value into the shifter circuit; and modifying the value loaded into the shifter circuit when the first address matches an address associated with a circuit block in the set of circuit blocks; bypassing the first defective circuit block in response to values stored in the shifter circuit; and connecting a first redundant circuit block in response to values stored in the shifter circuit.
 20. A method of replacing defective circuit blocks with redundant circuit blocks, the method comprising the steps of: identifying a first address of a first defective circuit block; identifying a second address of a second defective circuit block; identifying a third address of a third defective circuit block; serially loading values into a shifter circuit, wherein the values are selected in response to the first, second and third addresses; bypassing the first, second and third defective circuit blocks in response to values stored in the shifter circuit; and connecting first, second and third redundant circuit blocks in response to values stored in the shifter circuit.
 21. The method of claim 20, wherein the step of serially loading values into the shifter circuit further comprises the steps of: storing the first address in a first register; storing the second address minus one in a second register; storing the third address minus two in a third register; sequentially comparing the first address, the second address minus one, and the third address minus two with addresses associated with a set of circuit blocks; loading a value into the shifter circuit; modifying the value loaded into the shifter circuit when the first address matches an address associated with a circuit block in the set of circuit blocks; modifying the value loaded into the shifter circuit when the second address minus one matches an address associated with a circuit block in the set of circuit blocks; modifying the value loaded into the shifter circuit when the third address minus two matches an address associated with a circuit block in the set of circuit blocks. 